[Fwd: Re: [Beowulf] Cell in HPC]

Christian Bell Christian.Bell at qlogic.com
Tue May 30 23:43:09 PDT 2006

This paper is a good read and represents a lot of work.

On Tue, 30 May 2006, Richard Walsh wrote:

> CELL is a data-parallel heavy weight pitted against the
> instruction-parallel multi-core alternatives in which the question
> of how latency should be hidden is being considered --underneath
> stacks of independent/atomic instuction blocks (threads) which may
> or may not come from the same program, or with in a pipeline of
> vector operations that stream data from memory.  Apps with
> partitionable data with some kind of non-random reference pattern
> (most HPC appls) favors data-parallelism and vectors, while work
> loads with more completely random references and the large thread
> counts (graphs algorthms) typical of the mixed user environment of
> servers favor the thread-level instruction parallelism.

Cell may not be the only reason to revisit user-controlled memory
hierarchies.  While a parallel discussion thread on this list
recently pegged the Woodcrest as the 'ideal' supercomputer chip, I'd
bring up that having Woodcrest share L2 cache presents a problem for
parallel applications.  It may be constructive for SIMD parallel
execution models to share instruction code, but splitting L2 data
across cores is bound to be a destructive use of the cache in any
data parallel model.  Obviously, user control of the cache is a large
hammer to address this one potential problem, but scientific
applications will likely face more adversity if newer commodity
processor "features" continue to favor the instruction-parallel
models you mention.  

    . . christian

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