[Beowulf] high-speed embedded DRAM

Ted Matsumura matsumura at gmail.com
Fri May 6 13:20:29 PDT 2005

The future was here back in the late '90s with embedded DRAM in high-end 
NICs, then in 2000 in niche processor chips. The programming interfaces to 
take advantage of this, and the standardization of externally cascaded 
high-speed engines (100's of millions of searches/sec through 64K blocks) is 
still not widely standardized and in some cases the DRAM requires more 
standby power than SRAM, but can be up to 2x faster than SRAM alternatives. 
Low-latency high-speed memory access has been a requirement in fast switches 
and routers, but the technology is applicable to HPC/cluster computing as 
  > This may well be the future. Small cores with ever growing "scratch"
space that uses explicit fetch/stores to main memory. Maybe some/most of
this will change from SRAM to a DRAM to make these local memories larger.
Whatever the case, main storage needs to find its way closer to the
processing core. Double/Quad pumped buses and 128-bit memory channels can
only take us so far.
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