[Beowulf] quad-core SPECfp2006: where are 4 FPresults/cycle ?

richard.walsh at comcast.net richard.walsh at comcast.net
Sat Oct 13 10:28:43 PDT 2007

-------------- Original message -------------- 
From: "Mikhail Kuzminsky" <kus at free.net> 

> In message from richard.walsh at comcast.net (Fri, 12 Oct 2007 20:50:08 
> +0000): 
> >Mikhail, 
> >I am not sure I fully understand what you are presenting here, but I 
> >might say that yes, at the FPU unit level the 2222 series AMD 
> >Opteron/Barcelona and the Intel Core2/Clovertown (and also Harpertown 
> >at 45 nm) are now more largely equivalent -- that is they both can 
> >execute 2, double-wide (2x64 bit) floats in certain FMA situtations 
> >simultaneously and/or in a pipeline. 
> .... 
> >Regards, 
> >rbw 
> >-- 
> Sorry, now I'm misunderstanding :-) 
> I thought that Opteron 2222 don't have Barcelona microarchitecture 
> (all the Barcelona's are 23xx or 83xx) and therefore can't perform 
> 4*64 bit FP results per cycle. Am I wrong ? 
Whoops ... ;-( ... I should have said 23XX.  That is the Barcelona generation. If you were talking about generation two, then what I said about a 64-bit serialize staging of the 128-bit wide SSE FPU operations applies.  Sorry, if I caused confusion.  My comments regarding near-floating-point functional unit equivalency should be confined to comparing the 23XX series Opteron with the Clovertown/Harpertown processors from Intel. The point about 3-wide versus 4-wide applies with all Opteron generations.
Dobray Utra,
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