FIX: 0.99L and timeouts

[Andrew Morton]

Andrew Morton wrote:
> 
> I'm also wondering why we're not clearing TxIntrUploaded in prev_entry
> for the other leg of the 'if' statement: where we're setting tx_full.
> 

Replying to myself again.  Sigh.

I've worked this one out.  If we clear TxIntrUploaded in the first leg
of the 'if' then we'll only take an interrpt when _all_ packets have
been uploaded, and there will be a tx gap while the CPU restarts the
netif layer and starts to queue up more packets.  SO the original code
is better: it'll generate an interrupt on the last-but-oneth queued
packet, thus providing some interleaving. A little optimisation.

> > Yes, I'm running full duplex. However, I had to modify both 0.99L and your
> > driver to get this: set 3c905C as IS_CYCLONE|HAS_NWAY and then comment out
> > one line in vortex_probe1:

I sent this suggestion through to a 905C owner who was having big
autoneg problems.  His reply this morning stated with "Cool!".  Looks
good.

-- 
-akpm-
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