Beowulf in a Box (fwd)

[Bob Glamm]

> > First, if I recall my PCI spec correctly, it is possible to configure
> > each PCI device with an address space.  It should be possible to give
> > each StrongARM module (CPU + PCI interface + memory) its own 
> > distinct physical address space outside of the memory of the host
> > machine.  In addition, this address space should probably be
> > uncacheable as well to the host computer for a first iteration.
> > 
> > This configuration would gives the StrongARM "array" a SMP/NUMA
> > flavor.  CPU-CPU transfers are simply done by writing into/reading
> > from the other CPUs address space.  This makes it either SMP
> > (for processors on the same PCI board) or NUMA (for processors
> 
> 	It's neat, but with just 32 bits for addressing we're getting a
> bit tight of space on x86.

32 CPUs each with 64MB of memory is 2G of memory - plenty of space
left over ;)

All kidding aside: in this kind of structure the most StrongARM
CPUs that you'd want to put in one machine is probably only 16-32
anyway.  You're right, it is a little tight on x86, but it could still
be done.

Consider a slight alteration to what I proposed though: say each
processor has 1G of memory associated with it, but only map 16MB or 32MB 
of that processor's memory into the address space of the host.  This
would be the shared memory for each processor - the rest would be
for local computation only.

-Bob