<div dir="ltr"><div>My bad. The license has been updated now</div><div><a href="https://www.theregister.co.uk/2018/08/23/intel_microcode_license/">https://www.theregister.co.uk/2018/08/23/intel_microcode_license/</a><br><br></div></div><br><div class="gmail_quote"><div dir="ltr">On Thu, 23 Aug 2018 at 20:11, John Hearns <<a href="mailto:hearnsj@googlemail.com">hearnsj@googlemail.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr"><div><a href="https://www.theregister.co.uk/2018/08/21/intel_cpu_patch_licence/" target="_blank">https://www.theregister.co.uk/2018/08/21/intel_cpu_patch_licence/</a></div><div><br></div><div><a href="https://perens.com/2018/08/22/new-intel-microcode-license-restriction-is-not-acceptable/" target="_blank">https://perens.com/2018/08/22/new-intel-microcode-license-restriction-is-not-acceptable/</a></div><div><br></div><div><br></div></div><br><div class="gmail_quote"><div dir="ltr">On Tue, 21 Aug 2018 at 16:18, Lux, Jim (337K) <<a href="mailto:james.p.lux@jpl.nasa.gov" target="_blank">james.p.lux@jpl.nasa.gov</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><br>
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On 8/21/18, 1:37 AM, "Beowulf on behalf of Chris Samuel" <<a href="mailto:beowulf-bounces@beowulf.org" target="_blank">beowulf-bounces@beowulf.org</a> on behalf of <a href="mailto:chris@csamuel.org" target="_blank">chris@csamuel.org</a>> wrote:<br>
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    On Tuesday, 21 August 2018 3:27:59 AM AEST Lux, Jim (337K) wrote:<br>
<br>
    > I'd find it hard to believe that Intel's CPU designers sat around<br>
    > implementing deliberate flaws ( the Bosch engine controller for VW model).<br>
<br>
    Not to mention that Spectre variants affected AMD, ARM & IBM (at least).<br>
<br>
    This publicly NSA funded research ("The Intel 80x86 processor architecture: <br>
    pitfalls for secure systems") from 1995 has an interesting section:<br>
<br>
    <a href="https://ieeexplore.ieee.org/document/398934/" rel="noreferrer" target="_blank">https://ieeexplore.ieee.org/document/398934/</a><br>
    <a href="https://pdfs.semanticscholar.org/2209/42809262c17b6631c0f6536c91aaf7756857.pdf" rel="noreferrer" target="_blank">https://pdfs.semanticscholar.org/2209/42809262c17b6631c0f6536c91aaf7756857.pdf</a><br>
<br>
    Section 3.10 - Cache and TLB timing channels<br>
<br>
    which warns (in generalities) about the use of MSRs and the use of instruction <br>
    timing as side channels.<br>
<br>
<br>
<br>
Such vulnerabilities have existed since the early days of computers.  As processors and use cases have gotten more complex they're harder to find.<br>
<br>
This is why back in "orange book" days there's the whole "system high" mode of operation - basically "air gap, you, or things you trust, are the only one on the machine"<br>
<br>
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