<html><head><meta http-equiv="Content-Type" content="text/html charset=windows-1252"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;"><div><br></div>> There is only a limited surface area per die and Xeon's are not small.<div><span style="font-family: Arial, FreeSans, Helvetica, sans-serif; font-size: 13.63636302947998px; line-height: 19.09090805053711px; background-color: rgb(255, 255, 255);"><br></span></div><div><span style="font-family: Arial, FreeSans, Helvetica, sans-serif; font-size: 13.63636302947998px; line-height: 19.09090805053711px; background-color: rgb(255, 255, 255);">Read the article again :- </span></div><div><span style="font-family: Arial, FreeSans, Helvetica, sans-serif; font-size: 13.63636302947998px; line-height: 19.09090805053711px; background-color: rgb(255, 255, 255);">"By sticking an FPGA on top of a Xeon and linking it via Quick Path Interconnect tech, Intel reckons it has a compelling product for large customers.</span><font face="Arial, FreeSans, Helvetica, sans-serif"><span style="line-height: 19px;">”</span></font></div><div><font face="Arial, FreeSans, Helvetica, sans-serif"><span style="background-color: rgb(255, 255, 255);"><span style="line-height: 19px;"><br></span></span></font></div><div><font face="Arial, FreeSans, Helvetica, sans-serif"><span style="background-color: rgb(255, 255, 255);"><span style="line-height: 19px;">So the FPGA is a separate die which happens to be in the same package as the Xeon, and connected by QPI (the coherence interconnect used between Xeon’s). So die area on the Xeon die isn’t the issue since this is two dice.</span></span></font></div><div><font face="Arial, FreeSans, Helvetica, sans-serif"><span style="background-color: rgb(255, 255, 255);"><span style="line-height: 19px;"><br></span></span></font></div><div><font face="Arial, FreeSans, Helvetica, sans-serif"><span style="background-color: rgb(255, 255, 255);"><span style="line-height: 19px;">The advantages over a PCIe connected FPGA are that this is only one socket and doesn’t use any PCIe lanes, and that the FPGA is right on the processor’s coherence fabric.</span></span></font></div><div><font face="Arial, FreeSans, Helvetica, sans-serif"><span style="background-color: rgb(255, 255, 255);"><span style="line-height: 19px;"><br></span></span></font><div apple-content-edited="true">
<div style="color: rgb(0, 0, 0); letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px; word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;">-- Jim<br>James Cownie <<a href="mailto:jcownie@gmail.com">jcownie@gmail.com</a>><br>Mob: +44 780 637 7146<br><a href="http://skiingjim.blogspot.com/">http://skiingjim.blogspot.com/</a><br><br><br><br></div>
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<br><div><div>On 20 Jun 2014, at 04:03, Joe Landman <<a href="mailto:landman@scalableinformatics.com">landman@scalableinformatics.com</a>> wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite">On 06/19/2014 10:52 PM, Adam DeConinck wrote:<br><blockquote type="cite">-----BEGIN PGP SIGNED MESSAGE-----<br>Hash: SHA512<br><br>This is interesting...<br><br><a href="http://www.theregister.co.uk/2014/06/18/intel_fpga_custom_chip/">http://www.theregister.co.uk/2014/06/18/intel_fpga_custom_chip/</a><br></blockquote><br><br><br>This is what tensilica did previously though. The issue that we had found playing with it (about a decade ago) was that the FPGA was too small to be useful for real computation. You could run effectively toy problems on it, but not more than that. Maybe this has changed significantly in the last decade, but I doubt it. There is only a limited surface area per die and Xeon's are not small.<br><br>I think the idea is great, but the pragamatic issues are really hard.<br><br>Not to mention the programmability bit.<br><br>Seriously, I've always thought of generating some sort of domain specific set of instructions tightly coupled to a processor would be an awesome way to build an accelerated processor unit. I've just not seen a big enough FPGA and enough support at the programming level to make this worth the effort. But its intriguing.<br><br><br><br>-- <br>Joseph Landman, Ph.D<br>Founder and CEO<br>Scalable Informatics, Inc.<br>email: <a href="mailto:landman@scalableinformatics.com">landman@scalableinformatics.com</a><br>web : <a href="http://scalableinformatics.com">http://scalableinformatics.com</a><br>twtr : @scalableinfo<br>phone: +1 734 786 8423 x121<br>cell : +1 734 612 4615<br>_______________________________________________<br>Beowulf mailing list, <a href="mailto:Beowulf@beowulf.org">Beowulf@beowulf.org</a> sponsored by Penguin Computing<br>To change your subscription (digest mode or unsubscribe) visit <a href="http://www.beowulf.org/mailman/listinfo/beowulf">http://www.beowulf.org/mailman/listinfo/beowulf</a><br></blockquote></div><br></div></body></html>