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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Arghh.. Slide 10.. no units on the scales. What is this, some sort of high school project? Or a marketing presentation?<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">In any case, is the “per iteration energy” measured for just the CPU, or does it include memory, bus interface, or network connections?<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Slide 11 has the comment that “ARM CPU is not the major power sink in the platform”..<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">This might be a case where 10 chickens are better than a single ox, if the goal is the rapid production of offspring or food.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">But I agree with Bogdan that raw processor speed doesn’t necessarily imply scaleable power consumption, etc.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">The enormous volumes of mobile devices does mean that whatever price you are getting those processors at is likely to be as low as it can be (that is, all the
“economies of scale” have been fully realized).<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">But, there’s a significant “per chip” cost for handling, socketing, assembly, etc. And that cost does not change very much with level of integration. You
get to the extreme where when you buy7400 SSI parts (or, for that matter microcontrollers) that the dominant cost is the package: e.g. a 6 pin package is cheaper than an 8 pin package with the same exact die inside; and mounting the 8 pin package requires
33% more solder paste, and so forth.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">That said, I think that these ideas are important to explore.. Slide 20 talks about the lack of ECC. Well, if you’re serious about exascale, you’ve got to
embed fault tolerance into the very fabric of the algorithm, rather than trying to glue it on afterwards with ECC, or network retries, or whatever.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Jim Lux<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">From:</span></b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif""> beowulf-bounces@beowulf.org [mailto:beowulf-bounces@beowulf.org]
<b>On Behalf Of </b>Bogdan Costescu<br>
<b>Sent:</b> Tuesday, May 28, 2013 7:36 AM<br>
<b>To:</b> Eugen Leitl<br>
<b>Cc:</b> Beowulf Mailing List; info@postbiota.org<br>
<b>Subject:</b> Re: [Beowulf] Are mobile processors ready for HPC?<o:p></o:p></span></p>
<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">On Mon, May 27, 2013 at 5:28 PM, Eugen Leitl <<a href="mailto:eugen@leitl.org" target="_blank">eugen@leitl.org</a>> wrote:<o:p></o:p></p>
<p class="MsoNormal">The researchers point to the history of less expensive chips bumping out<br>
faster but higher-priced processors in high-performance systems. In 1993, the<br>
list of the world's fastest supercomputers, known as the Top500, was<br>
dominated by systems based on vector processors. They were nudged out by less<br>
expensive RISC processors like IBM's Power chip, whose use in supercomputers<br>
peaked early in the past decade. The RISC chips in turn were eventually<br>
replaced by cheaper commodity processors like Intel's Xeon and Advanced Micro<br>
Devices' Opteron, which today are used in more than 400 supercomputers on the<br>
Top500 list.<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal" style="margin-bottom:12.0pt">Please allow me to be skeptical.<br>
<br>
The presentation again tells that the FP performance is at least one order of magnitude lower for mobile processors than for desktop/server ones. I found nice the comparison of bandwidth/FLOPs, which to me suggests that the parallel scalability is comparable.
Putting these two together means I get my computational results with the same scalability but at least 10x slower. To get the same performance, and assuming an ideal further scaling, I would need at least 10x more processors, which will consume at least 10x
more power and cost at least 10x more. Hmmmm, I simply don't see the advantage... same one ox versus 10 chicken we discussed many times. How many ARM cores would one need to reach exaflops level ?<br>
<br>
I also don't see how the history repeats in this case. Around year 2000, desktop CPUs were at similar levels of performance with RISC ones, and at a fraction of cost. But this doesn't hold for the current comparison.<o:p></o:p></p>
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<p class="MsoNormal">One thing that I miss from the presentation is the power and cost of interconnects. The current fast interconnects would allow a setup involving many CPUs/nodes to scale further. But the current fast interconnects are quite power hungry
and expensive. Would anyone couple a 1W CPU with a 10W NIC (ballpark figures) ? Or a 50EUR CPU with a 500EUR NIC (again, ballpark figures) ? I wouldn't...<o:p></o:p></p>
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<p class="MsoNormal">I can imagine mobile processors used in test clusters - good for teaching about cluster architecture, development and especially scalability, with low power and low cost. Embody the "cluster under my desk" concept. Also in massive parallel
file systems - like a HDD which doesn't have an onboard SATA controller exposing a SATA interface to the outside, but a processor talking directly to the drive electronics, exposing a Gigabit Ethernet (or better...) interface and running your favorite parallel
FS software. Or similar for a RAM-based setup, where each memory module has one or more processing cores attached to it. For such applications, the reasonable memory access speed coupled with the low cost and low power requirements of mobile processors are
indeed an advantage. As long as there is not much FP involved...<o:p></o:p></p>
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<p class="MsoNormal">Cheers,<o:p></o:p></p>
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<p class="MsoNormal">Bogdan<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal" style="margin-bottom:12.0pt"><o:p> </o:p></p>
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<p class="MsoNormal">On Mon, May 27, 2013 at 5:28 PM, Eugen Leitl <<a href="mailto:eugen@leitl.org" target="_blank">eugen@leitl.org</a>> wrote:<o:p></o:p></p>
<p class="MsoNormal"><br>
<a href="http://www.pcworld.com/article/2039798/smartphone-chips-could-replace-server-processors-in-hpc-researchers-say.html" target="_blank">http://www.pcworld.com/article/2039798/smartphone-chips-could-replace-server-processors-in-hpc-researchers-say.html</a><br>
<br>
Smartphone chips may power servers, researchers say<br>
<br>
Agam Shah, IDG News Service<br>
<br>
@agamsh May 25, 2013 12:50 PMprint<br>
<br>
Looking at historical trends and performance benchmarks, a team of<br>
researchers in Spain have concluded that smartphone chips could one day<br>
replace the more expensive and power-hungry x86 processors used in most of<br>
the world's top supercomputers.<br>
<br>
"History may be about to repeat itself," researchers at the Barcelona<br>
Supercomputing Center wrote in a paper titled "Are mobile processors ready<br>
for HPC?" The paper was presented at the EDAworkshop13 in Dresden, Germany,<br>
this month.<br>
<br>
Chip Wars<br>
<br>
The researchers point to the history of less expensive chips bumping out<br>
faster but higher-priced processors in high-performance systems. In 1993, the<br>
list of the world's fastest supercomputers, known as the Top500, was<br>
dominated by systems based on vector processors. They were nudged out by less<br>
expensive RISC processors like IBM's Power chip, whose use in supercomputers<br>
peaked early in the past decade. The RISC chips in turn were eventually<br>
replaced by cheaper commodity processors like Intel's Xeon and Advanced Micro<br>
Devices' Opteron, which today are used in more than 400 supercomputers on the<br>
Top500 list.<br>
<br>
The transitions had a common thread, the researchers wrote: Microprocessors<br>
killed the vector supercomputers because they were "significantly cheaper and<br>
greener," they said.<br>
<br>
"Mobile processors are not faster ... but they are significantly cheaper,"<br>
the researchers wrote.<br>
<br>
]SNIP]<br>
<br>
<a href="http://www.montblanc-project.eu/sites/default/files/publications/Are%20mobile%20processors%20ready%20for%20HPC.pdf" target="_blank">http://www.montblanc-project.eu/sites/default/files/publications/Are%20mobile%20processors%20ready%20for%20HPC.pdf</a><br>
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