<html><head></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space; "><br><div><div>New thread, new disclaimer: I work for Intel and sometimes even on Intel(r) Xeon Phi(tm) co-processor...</div><div><br></div><div>On 22 Mar 2013, at 16:14, Mark Hahn wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite"><div><blockquote type="cite">No ECC might be an issue.<br></blockquote><br>Phi definitely has a mode to enable ECC for onboard dram,<br>similar to how Nvidia and AMD do it (somewhat reduced <br>performance and capacity, since the interface is a power<br>of two bits wide.) </div></blockquote><div>Correct. There is ECC, and it is enabled by default. All Intel's published benchmarks</div><div>are supposed to be run with ECC enabled and a statement to that effect ought to</div><div>be included. (There should *certainly* be a statement if it is *not* enabled!)</div><div>Of course Intel can't control how owners of the card choose to run or report their results.</div><br><blockquote type="cite"><div>it says here:<br><a href="http://software.intel.com/en-us/articles/case-study-achieving-superior-performance-on-black-scholes-valuation-computing-using">http://software.intel.com/en-us/articles/case-study-achieving-superior-performance-on-black-scholes-valuation-computing-using</a><br>that Phi has ECC on L2 as well. (afaik it's fairly common<br>to do only parity on L1, especially for inclusive caches, <br>since corrupted lines can be refetched from the L+1 cache.)<br><br><blockquote type="cite">Public information states approximately 2 SP<br></blockquote><blockquote type="cite">ops per DP op. Sounds like the SIMD registers can do both, like a normal<br></blockquote><blockquote type="cite">x86 chip.</blockquote></div></blockquote><div>Exactly. </div><div>A little Googling finds <a href="http://www.theregister.co.uk/2012/11/12/intel_xeon_phi_coprocessor_launch/">http://www.theregister.co.uk/2012/11/12/intel_xeon_phi_coprocessor_launch/</a></div><div>for instance, which is accurate AFAICT and says </div><div>"<span style="color: rgb(0, 0, 0); font-variant: normal; letter-spacing: normal; line-height: 16.799999237060547px; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; -webkit-text-size-adjust: auto; -webkit-text-stroke-width: 0px; background-color: rgb(255, 255, 255); display: inline !important; float: none; ">This VPU is capable of processing eight 64-bit double-precision floating point operations or </span></div><div><span style="color: rgb(0, 0, 0); font-variant: normal; letter-spacing: normal; line-height: 16.799999237060547px; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; -webkit-text-size-adjust: auto; -webkit-text-stroke-width: 0px; background-color: rgb(255, 255, 255); display: inline !important; float: none; ">sixteen 32-bit single-precision operations in one clock cycle."</span></div><div><span style="color: rgb(0, 0, 0); font-variant: normal; letter-spacing: normal; line-height: 16.799999237060547px; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; -webkit-text-size-adjust: auto; -webkit-text-stroke-width: 0px; background-color: rgb(255, 255, 255); display: inline !important; float: none; ">Not wanting to feed the troll, but I'm not clear why Vincent thinks that a 2x SP </span></div><div><span style="color: rgb(0, 0, 0); font-variant: normal; letter-spacing: normal; line-height: 16.799999237060547px; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; -webkit-text-size-adjust: auto; -webkit-text-stroke-width: 0px; background-color: rgb(255, 255, 255); display: inline !important; float: none; ">to DP ratio is so bad, when some Googling suggests that </span></div><div><span style="color: rgb(0, 0, 0); font-variant: normal; letter-spacing: normal; line-height: 16.799999237060547px; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; -webkit-text-size-adjust: auto; -webkit-text-stroke-width: 0px; background-color: rgb(255, 255, 255); display: inline !important; float: none; ">the ratio for </span><span style="color: rgb(0, 0, 0); font-variant: normal; letter-spacing: normal; line-height: 16.799999237060547px; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; -webkit-text-size-adjust: auto; -webkit-text-stroke-width: 0px; background-color: rgb(255, 255, 255); display: inline !important; float: none; ">various GPUs seems to be rather higher (i.e. more SP biased).</span></div><br><blockquote type="cite"><div>Phi implements standard x86 integer, x87 (!), and the Phi-specific<br>512b-wide mode. (I wish they'd just call it MMX512 or something, <br>rather than inventing a new, inconsistent name. MMX, SSE, SSE2, SSE3,<br>but then SSSE3, then back to SSE4, then AVX and now IMICPHIAVX++ ;)</div></blockquote><blockquote type="cite"><div>although I'm excited to get my hands on a Phi, I can't help thinking<br>about how it seems a little rushed. not supporting any of the *SSE*<br>levels, for instance.</div></blockquote>It would clearly be nice if the Phi had all of those features, but</div><div>* You wouldn't get performance if you used them</div><div>* They take space; how many cores would you give up to have them?</div><div> (Remembering that for the codes you're serious about you won't be using them...)</div><div><br></div><div><div><span class="Apple-style-span" style="border-collapse: separate; color: rgb(0, 0, 0); font-family: Helvetica; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; -webkit-border-horizontal-spacing: 0px; -webkit-border-vertical-spacing: 0px; -webkit-text-decorations-in-effect: none; -webkit-text-size-adjust: auto; -webkit-text-stroke-width: 0px; font-size: medium; "><span class="Apple-style-span" style="border-collapse: separate; color: rgb(0, 0, 0); font-family: Helvetica; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; -webkit-border-horizontal-spacing: 0px; -webkit-border-vertical-spacing: 0px; -webkit-text-decorations-in-effect: none; -webkit-text-size-adjust: auto; -webkit-text-stroke-width: 0px; font-size: medium; "><div style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space; "><div><div style="margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; "><font face="Helvetica" size="3" style="font: normal normal normal 12px/normal Helvetica; ">--</font></div><div style="margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; "><font face="Helvetica" size="3" style="font: normal normal normal 12px/normal Helvetica; ">-- Jim</font></div><div style="margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; "><font face="Helvetica" size="3" style="font: normal normal normal 12px/normal Helvetica; ">--</font></div><div style="margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; "><font face="Helvetica" size="3" style="font: normal normal normal 12px/normal Helvetica; ">James Cownie <<a href="mailto:jcownie@cantab.net">jcownie@cantab.net</a>></font></div><br></div></div></span></span><br class="Apple-interchange-newline"></div></div></body></html>