rbw that is actually true 4th quater of this year intel is release its first 8 core with hyperthreading processor to the xenon market. amd currently already has their 6 core out.<div><br></div><div>i understand the reasoning you made about recycling them David, which saves the company money as a whole on manufacturing especially since they wont need another plant to prossibly produce the lower end product.<br>
<br><div class="gmail_quote">On Fri, Aug 21, 2009 at 12:35 AM, <span dir="ltr"><<a href="mailto:richard.walsh@comcast.net">richard.walsh@comcast.net</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex;">
<div><div style="font-family:Arial;font-size:12pt;color:#000000"><div class="im"><br><br><br><br>>----- Original Message -----<br>>From: "David Mathog" <<a href="mailto:mathog@caltech.edu" target="_blank">mathog@caltech.edu</a>><br>
>To: <a href="mailto:beowulf@beowulf.org" target="_blank">beowulf@beowulf.org</a><br>>Sent: Thursday, August 20, 2009 2:33:38 PM GMT -06:00 US/Canada Central<br>>Subject: [Beowulf] Re: amd 3 and 6 core processors<br>
><br>>Jonathan Aquilina <<a href="mailto:eagles051387@gmail.com" target="_blank">eagles051387@gmail.com</a>> wrote:<br>><br>>> a friend of mine told me that the amd tri cores were quads with one core<br>
>> disabled?<br>><br>>Probably. It will often be the case that the disabled core is<br>>defective, maybe not fully dead, but it did not pass all of its tests. <br>>It is common practice to recycle multicore CPUs with one bad CPU and<br>
>sell it as a lower performance part. Similarly, chips that won't run at<br>>full speed, but will pass all tests at a lower speed, may be stamped as<br>>a lower performance part and shipped as that. It makes good business<br>
>sense to do this since it lets them recover the otherwise wasted<br>>production costs on these partially defective devices. They may also<br>>disable the 4th core even if works perfectly, and sell it as a 3 core<br>
>device, when they have an order for the tricore that needs to be shipped<br>>and not enough quadcore chips on hand with one bad core to fill it.<br><br></div><div>Many good points above and in Greg's earlier note. Its all about yield</div>
<div>and what you can fit on the chip at a given line width.</div><div><br></div><div>In the past, binning by clock was the primary (only?) choice to bring up</div><div>yields. As chips have grown in size and evolved toward multi-core, </div>
<div>degrading cores has been a economic side-benefit. IBM was one of</div><div>the first to use this approach (first with dual-core too), when they sold dual-core</div><div>Power series chips with one core disable to give the remaining core</div>
<div>maximum bandwidth. There is little benefit in developing processing</div><div>for real 2, 3, 4, 5, 6, 7, ... etc. core chips. Better to start with a standard </div><div>process and core-count, and degrade it to fill lower power and performance</div>
<div>bins. The Nehalem micro-architecture is available as a dual core offering. It</div><div>is not clear to me (someone here may know), whether this is not just a</div><div>degraded quad-core, or a true dual core. This pinout is different, so</div>
<div>perhaps it is a true dual-core. I would also like to know how Intel and</div><div>AMD are disabling/degrading the cores. They very like have built</div><div>in circuits that they can "burn out" to ensure physical incapacity. Still,</div>
<div>perhaps it is done another way. With Nehalem and its on-chip power</div><div>management unit, dynamic "soft" disabling may be all that is needed.</div><div><br></div><div>As folks here are I am sure aware, Intel will have a true 8-core offering</div>
<div>in the next 3 to 6 months which puts them in a position to offer 5 and</div><div>7 core degraded processors as well. </div><div><br></div><div>rbw</div></div></div><br>_______________________________________________<br>
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<br></blockquote></div><br><br clear="all"><br>-- <br>Jonathan Aquilina<br>
</div>