[Beowulf] Intel combines Xeon and FPGA in a single socket
jcownie at gmail.com
Fri Jun 20 11:18:20 PDT 2014
> There is only a limited surface area per die and Xeon's are not small.
Read the article again :-
"By sticking an FPGA on top of a Xeon and linking it via Quick Path Interconnect tech, Intel reckons it has a compelling product for large customers.”
So the FPGA is a separate die which happens to be in the same package as the Xeon, and connected by QPI (the coherence interconnect used between Xeon’s). So die area on the Xeon die isn’t the issue since this is two dice.
The advantages over a PCIe connected FPGA are that this is only one socket and doesn’t use any PCIe lanes, and that the FPGA is right on the processor’s coherence fabric.
James Cownie <jcownie at gmail.com>
Mob: +44 780 637 7146
On 20 Jun 2014, at 04:03, Joe Landman <landman at scalableinformatics.com> wrote:
> On 06/19/2014 10:52 PM, Adam DeConinck wrote:
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>> This is interesting...
> This is what tensilica did previously though. The issue that we had found playing with it (about a decade ago) was that the FPGA was too small to be useful for real computation. You could run effectively toy problems on it, but not more than that. Maybe this has changed significantly in the last decade, but I doubt it. There is only a limited surface area per die and Xeon's are not small.
> I think the idea is great, but the pragamatic issues are really hard.
> Not to mention the programmability bit.
> Seriously, I've always thought of generating some sort of domain specific set of instructions tightly coupled to a processor would be an awesome way to build an accelerated processor unit. I've just not seen a big enough FPGA and enough support at the programming level to make this worth the effort. But its intriguing.
> Joseph Landman, Ph.D
> Founder and CEO
> Scalable Informatics, Inc.
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