[Beowulf] Is there really a need for Exascale?

Einar Rustad er at numascale.com
Thu Nov 29 15:24:56 PST 2012


On 29. nov. 2012, at 15:19, "Lux, Jim (337C)" <james.p.lux at jpl.nasa.gov> wrote:

> 
> 
> On 11/28/12 11:46 PM, "Eugen Leitl" <eugen at leitl.org> wrote:
> 
>> On Thu, Nov 29, 2012 at 01:14:39AM -0500, Mark Hahn wrote:
>> 
>> I've been waiting for cache to die and be substituted by
>> on-die SRAM or MRAM. Yet to happen, but if it happens,
>> it will be with embedded-like systems.
> 
> 
> When running, SRAM consumes a lot more power and space than almost any
> kind of DRAM.  2-4 transistors per cell vs 1, if nothing else.
> A big problem is that the CMOS process for dense, low power, fast RAM is
> different than what you want to use for a CPU. And even between DRAM and
> SRAM there's a pretty big difference. (trenches, etc.)

Modern SRAM cells are normally 6 transistors per cell. DRAM is 1. An SRAM cell is a flip-flop and
keeps the information as long as power is on.  The transistors should be as fast as possible; i.e. they 
can be made in the same way as logic transistors.
DRAM stores the data in a capacitor. Leakage should be minimal and capacitance 
relatively large to avoid too frequent refreshing. These characteristics are different from what is 
needed to make fast logic and SRAM so combining processing and DRAM on the same die is problematic.
I noticed the other day that IBM has made a new processor with embedded DRAM for a large L3 cache, 
a move I find quite interesting for a general purpose processor.

> 
> 
>> 
>>>> production density.  Consumer markets have the advantage of enormous
>>>> volumes to spread the very high non-recurring-engineering cost over.
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