[Beowulf] Is there really a need for Exascale?
eugen at leitl.org
Thu Nov 29 06:47:53 PST 2012
On Thu, Nov 29, 2012 at 02:19:26PM +0000, Lux, Jim (337C) wrote:
> On 11/28/12 11:46 PM, "Eugen Leitl" <eugen at leitl.org> wrote:
> >On Thu, Nov 29, 2012 at 01:14:39AM -0500, Mark Hahn wrote:
> >I've been waiting for cache to die and be substituted by
> >on-die SRAM or MRAM. Yet to happen, but if it happens,
> >it will be with embedded-like systems.
> When running, SRAM consumes a lot more power and space than almost any
> kind of DRAM. 2-4 transistors per cell vs 1, if nothing else.
Yes, but we're talking cache. Cache is SRAM with extra logic.
Even a cache hit is slower than it would take to access on-die
SRAM. Cache coherency doesn't scale due to relativistically
constrained signalling. There also cannot be any such thing
as a global memory, unless you want it to be slow and spend
a lot of silicon real estate to make multiple writes to the
same location consistent.
> A big problem is that the CMOS process for dense, low power, fast RAM is
> different than what you want to use for a CPU. And even between DRAM and
> SRAM there's a pretty big difference. (trenches, etc.)
This is why we need stacked memories. Notice that MRAM might be compatible
with CPU fabbing processes. ST-MRAM
should have very good scaling in terms of performance and power
dissipation and can potentially be fabricated on top of an
ordinary CPU core http://www.cs.utexas.edu/~cart/publications/tr01-36.pdf
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