No subject


Tue Nov 9 01:00:01 PST 2010


posted here, the cache protocol allows sharing data between the CPUs
via the northbridge directly. With direct access to eachother's caches
MOESI is required. However, it would seem to me that to employ this
high speed inter-cpu communications system, you'd need some specific
code. Or am I thinking of this wrong - say for Gromacs, which uses
shared memory on SMP boards (well, lam mpi does) for communication,
if the shared memory area is in one CPU's cache, the other  CPU
can then access it directly from that cache? This would speed things
up a fair bit I would expect.

Does anyone have benchmarks on MP processors for Gromacs, MPQC and
G98?

/kc

> 
> 3DNow! Professional is actually Intel's SSE, which Intel's compiler can
> generate vectorized code to take advantage of.
> 
> Rayson
> 
> 
> --- Velocet <math at velocet.ca> wrote:
> > What packages support MOESI and 3DNow!Professional? When will they?
> > 
> > /kc
> > -- 
> > Ken Chase, math at velocet.ca  *  Velocet Communications Inc.  * 
> > Toronto, CANADA 
> > _______________________________________________
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-- 
Ken Chase, math at velocet.ca  *  Velocet Communications Inc.  *  Toronto, CANADA 



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