[Beowulf] Re: amd 3 and 6 core processors

richard.walsh at comcast.net richard.walsh at comcast.net
Thu Aug 20 15:35:34 PDT 2009





>----- Original Message ----- 
>From: "David Mathog" <mathog at caltech.edu> 
>To: beowulf at beowulf.org 
>Sent: Thursday, August 20, 2009 2:33:38 PM GMT -06:00 US/Canada Central 
>Subject: [Beowulf] Re: amd 3 and 6 core processors 
> 
>Jonathan Aquilina <eagles051387 at gmail.com> wrote: 
> 
>> a friend of mine told me that the amd tri cores were quads with one core 
>> disabled? 
> 
>Probably. It will often be the case that the disabled core is 
>defective, maybe not fully dead, but it did not pass all of its tests. 
>It is common practice to recycle multicore CPUs with one bad CPU and 
>sell it as a lower performance part. Similarly, chips that won't run at 
>full speed, but will pass all tests at a lower speed, may be stamped as 
>a lower performance part and shipped as that. It makes good business 
>sense to do this since it lets them recover the otherwise wasted 
>production costs on these partially defective devices. They may also 
>disable the 4th core even if works perfectly, and sell it as a 3 core 
>device, when they have an order for the tricore that needs to be shipped 
>and not enough quadcore chips on hand with one bad core to fill it. 


Many good points above and in Greg's earlier note. Its all about yield 
and what you can fit on the chip at a given line width. 


In the past, binning by clock was the primary (only?) choice to bring up 
yields. As chips have grown in size and evolved toward multi-core, 
degrading cores has been a economic side-benefit. IBM was one of 
the first to use this approach (first with dual-core too), when they sold dual-core 
Power series chips with one core disable to give the remaining core 
maximum bandwidth. There is little benefit in developing processing 
for real 2, 3, 4, 5, 6, 7, ... etc. core chips. Better to start with a standard 
process and core-count, and degrade it to fill lower power and performance 
bins. The Nehalem micro-architecture is available as a dual core offering. It 
is not clear to me (someone here may know), whether this is not just a 
degraded quad-core, or a true dual core. This pinout is different, so 
perhaps it is a true dual-core. I would also like to know how Intel and 
AMD are disabling/degrading the cores. They very like have built 
in circuits that they can "burn out" to ensure physical incapacity. Still, 
perhaps it is done another way. With Nehalem and its on-chip power 
management unit, dynamic "soft" disabling may be all that is needed. 


As folks here are I am sure aware, Intel will have a true 8-core offering 
in the next 3 to 6 months which puts them in a position to offer 5 and 
7 core degraded processors as well. 


rbw 
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