[Beowulf] Multicore Is Bad News For Supercomputers

[Eugen Leitl]

On Sat, Dec 06, 2008 at 07:36:44AM +1100, Michael Brown wrote:

> I think this needs to be elaborated a little for those who don't know the 
> layout of SDRAM ...

Thank you, most useful information.

[SNIP]

I don't think this is very applicable to custom DRAM stacked
on top of core, or SRAM/eDRAM (eventually MRAM?) in the core 
(e.g. like the Cell does it).

There the most natural way is structure it into very wide words,
and access it a that way. Add an array of ALUs on top of it
along with shifts, n-bit swaps and the like and you'll get a very 
beefy machine on each die.

Add a router to each die, and you've got potential for wafer-scale
integration, by routing around dead dies from production or dynamically
remapping failed grains during operation.

This might not look like commodity, but eventually graphics
accelerators must go there due to memory bandwidth limitations,
and eventually CPUs will converge.
 
-- 
Eugen* Leitl <a href="http://leitl.org">leitl</a> http://leitl.org
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