[Beowulf] Tilera to Introduce 64-Core Processor

Peter St. John peter.st.john at gmail.com
Thu Oct 18 07:45:02 PDT 2007


DLP? Wiki has entries for Indtruction Level Parallelism and Thread LP (alsom
Memory LP) but not DLP?
Peter

>Perhaps you are refering to the TRIPS Polymorphic Processor from U of Texas
which can be configured to favor ILP, DLP, or TLP application types.   I
think I sent out this reference a while back.  It should be in the
archives.

>  rbw
>
>
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