[Beowulf] Tilera to Introduce 64-Core Processor
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Peter St. John peter.st.john at gmail.comThu Oct 18 07:45:02 PDT 2007
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DLP? Wiki has entries for Indtruction Level Parallelism and Thread LP (alsom Memory LP) but not DLP? Peter >Perhaps you are refering to the TRIPS Polymorphic Processor from U of Texas which can be configured to favor ILP, DLP, or TLP application types. I think I sent out this reference a while back. It should be in the archives. > rbw > > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.scyld.com/pipermail/beowulf/attachments/20071018/6801eaeb/attachment.html
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