[Beowulf] Teraflop chip hints at the future

[Richard Walsh]

Mark Hahn wrote:
>> It looked like it did IEEE754 doubles.  Any Intel types out there to 
>> confirm/deny?
> singles:
>
> http://www.pcper.com/article.php?aid=363
>
> IMO, the chip is mainly interesting to explore how much we can abandon
> the von Neumann architecture as a whole, rather than stupidly putting
> more and more of them onto a chip.  after all, the nearest-neighbor
> latency (125 ps!) is comparable to cache or even register-file.
Yes, but how much does it really abandon von Neumann.  It is just a lot
of little von Neumann machines unless the mesh is fully programmable
and the DRAM stacks can source data for any operation on any cpu as
the application's data flows through the application kernel(s) however it
is laid out across the chip.  And in that case it is a multi-core ASIC 
emulating
an FPGA ... why not just use an FPGA ... ;-) ... and avoid wasting all those
hard-wired functional units that won't be needed for this or that particular
kernel. 

To abondon von Neuman you have to abandon the cyclic re-referencing of
the same store and "store" results in-wire or along the path defined by 
a code
customed data-flow processor.  Them you eliminate as much of the memory
reference latency as possible.  The problem/question is how much of the
given applications kernel can you swallow on a single chip before having to
got back to some kind of general memory for data or instructions.  I 
like the idea
of an array of FPGA cores on a chip (super-FPGA model).  Less wasted
hardware.  In some sense, these super, multi-mini-core designs are another
ASIC hammer looking for a nail.  Fixed instruction architectures ultimately
waste hardware.   Why not program the processor instead of instructions
for a predefined one-size fits all ASIC?

But I suppose the industry has to get there somehow ... and super-multi-mini
core is one way.  The RAW processor already mapped out the benefits of
this approach, but I think they are just a mile post on the way to a 
super FPGA
model.  I think every one should be learning to program in Mitrion-C ... 
;-).

rbw

-- 

Richard B. Walsh

"The world is given to me only once, not one existing and one
 perceived. The subject and object are but one."

Erwin Schroedinger

Project Manager
Network Computing Services, Inc.
Army High Performance Computing Research Center (AHPCRC)
rbw at ahpcrc.org  |  612.337.3467

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