[Beowulf] Re: vectors vs. loops
diep at xs4all.nl
Tue May 3 17:25:44 PDT 2005
At 05:34 PM 5/3/2005 +0200, Alan Louis Scheinine wrote:
>There are very few types of computers with an adeguate
>bandwidth to main memory to keep the vector units busy,
>NEC is one of the few.
>This thread of discussion has evolved, so that now there are
>estimates of how much scientific code can be vectorized.
>When indirect addressing does not impede vectorization, it is
>my impression that alot of code can be vectorized but the
>typical real-world problems have vectors much larger than
>L1 cache and often much larger than L2 cache.
>If the question boils down to the choice of hardware,
>the amount of code that is vectorizable may not be the
>key question, but rather: for any proposed vector hardware
>what is the proposed solution for the memory bandwidth problem
>when using that hardware?
This isn't at all the problem. So to speak for highend processors even a
medium engineer can add a few on die memory controllers to solve the
bandwidth problem. 1 for every few cores.
The focus IMHO really should be making cores that can execute a lot of
instructions simultaneously WITH a branch prediction table at the core.
Shifting the problem to RAM is IMHO not a good idea.
To give a simple bio-informatics example, a small dataset of a few hundreds
of kilobytes, already generates enough data.
So to speak a bit big L3 cache on chip already eliminates for such matrice
invariant calculations the need more or less for RAM.
The fastest way to multiply arrays, without rounding off (as that will give
errors) is still pretty slow compared to the total data size that such an
So the weak chain really is the number of calculations the hardware
delivers, not the memory bandwidth.
The memory bandwidth you simply design to the maximum speed the chip can
get, not vice versa.
The real weak chain is therefore the number of gflops a chip gets. The rest
is pretty easily solvable.
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