[Beowulf] more news on the Cell
diep at xs4all.nl
Thu Jun 30 17:35:24 PDT 2005
Regrettably nothing new there.
We already knew it would have 8 SPE's.
There is a lot of questions remaining :
a) how many integer execution units does it have within each SPE?
b) "up to 8 floating point instructions per cycle" sounds very
impressive for those who do vector work,
however elsewhere i read it has a 5 cycle 6 issue SRAM cache.
How many of those floating point units can do both multiplication
Correct me if i'm wrong.
In case of simplistic matrixcalculations or something similar
that means each 4 cycles it can do 3 multiplies, it needs to load 6
floats from SRAM and that can give 2 multiplies.
Only if you are real lucky already in register you have a
value to multiply with. That means it can do in case of not being lucky,
that it is getting less than 1 flop per cycle per SPU.
Let's optimistically round it off to 1 flop per cycle (butterfly fmul's):
1 * 4Ghz * 8 SPE's = 32 gflop @4Ghz.
Still awesome, but not close to the claimed 256+ gflop previously.
Finally what i'm really missing is its price if you want to have CELL
processors without needing to cluster PS3's.
At 04:12 PM 6/30/2005 +0200, Eugen Leitl wrote:
>also, see http://www.research.scea.com/research/html/CellGDC05/index.html
>Eugen* Leitl <a href="http://leitl.org">leitl</a>
>ICBM: 48.07100, 11.36820 http://www.leitl.org
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