gromacs benchmark and quad Xeons

[Richard Walsh]

On Tue, Jun 18, 2002 at 02:14:02PM -0400, Velocet wrote:
...
> Are the original rpms for gromacs which are generally compiled for P2/MMX
> going to be absolutely the worst possible situation for a Xeon? Or should
> they work relatively near best-speed (minus missing SSE and SSE2 instructions,
> though I dont even know if GCC gives the full set of either for a hand
> compile). 
> 
> What's wrong here? Any ideas?

My first reaction is to wonder what your memory foot print is ...
the bandwidth of all quad's I have seen (except the ES-45 with 
Compaq's typhoon chipset and cross-bar) has been lousy. If you
are not running mostly/completely in cache this could be an
issue.  Competition from all four CPUs for bandwidth could kill
performance. 

Have your tried running on one CPU? Can you shrink the test
case to make sure it is cache and then look at the performance?
How does stream performanc on this quad?


rbw
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