Dual Athlon Progress. (fwd)
Many of your questions may have already been answered in earlier discussions or in the FAQ. The search results page will indicate current discussions as well as past list serves, articles, and papers.
Eugene Leitl Eugene.Leitl at lrz.uni-muenchen.deWed Jun 13 02:14:12 PDT 2001
- Previous message: [Multiple node groups in Scyld]
- Next message: liquid nitrogen cooling a possibility?
- Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]
-- Eugen* Leitl ______________________________________________________________ ICBMTO : N48 10'07'' E011 33'53'' http://www.lrz.de/~ui22204 57F9CFD3: ED90 0433 EB74 E4A9 537F CFF5 86E7 629B 57F9 CFD3 ---------- Forwarded message ---------- Date: 13 Jun 2001 02:58:17 -0600 From: Eric W. Biederman <ebiederman at lnxi.com> To: LinuxBIOS <linuxbios at lanl.gov> Subject: Dual Athlon Progress. I'm making head way. I have solved an annoying bug where the system would somtimes crass at boot. The fix was to initialize some more registers. Totally unitialized regiterst that if you reboot fast enough from since your last boot are fun. I have tracked down my IOAPIC problems and it appears the proper IOAPIC initialization is to explicitly disable all of it's interrupts. I'd verify that by booting into linux but something I did has broken DMA... And since one of the drivers I have compiled in does DMA during it's initialization it fails... Has anyone seen linuxBIOS to break DMA before? Anyway I'm going through everything one step at a time making certain not to leave any details left undone. Hopefully I'll get to the DMA issue soon. There is so much left to do in the ram initialization that it may take a while. I'm making progress in finish the SPD code. Ram sizing has been done for a while, but now I need to get all of the timing registers programmed right. The Athlon is annoying you can't initialize the cache and use it for ram. There has to be something better than assembly to write this mess in. Anyway. I have have registered versus non registered DIMMS handled. The first pass at automatic CAS latency detection, written. And front side bus clock speed changes written. There are still probably a dozen more timing registers to go, and a lot of error cases to handle yet. With some luck I should get this done tommorrow. Currently raminit.inc is at 1000 lines and growing... DDR SDRAM is just like SDRAM for as far as the SPD bytes are concerned. But with stronger requirements that you use the SPD bytes. I'm currently using 17 SPD bytes, and it looks like I'll probably wind up using at least 6 more. I don't think I even want to try fitting this code into a doc and only 512 bytes... My totally unreasonable goal is to have the code in good enough shape to start committing it into the linuxBIOS tree by friday. The current outstanding bugs are: - The second CPU doesn't seem to want to start up. I've traced this pretty thoroughly but I'm not certain what is wrong yet. I might have to implement cpu reset code in linuxBIOS. - DMA doesn't work. Now to go to bed so I am worth something tommorrow. Eric
- Previous message: [Multiple node groups in Scyld]
- Next message: liquid nitrogen cooling a possibility?
- Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]
More information about the Beowulf mailing list
