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Eugene Leitl Eugene.Leitl at lrz.uni-muenchen.deFri Feb 23 04:25:48 PST 2001
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On Fri, 23 Feb 2001, Alan Scheinine wrote: > On the Tera CPU, the context switch is not costly whereas the CPU > with leading-edge performance is costly. I wasn't proposing fat CPUs. Tera CPU switches context every instruction, resulting in suboptimal single-thread performance. Context switches are always costly, you either pay in latency or in hardware (by having several instances of an engine). High-clock CPUs are necessarily primitive, and memory bottleneck disappears with kBit wide buses to embedded memory. Given low (essentially relativistical latency constrained) messaging overhead, you can always lay out a pipeline spatially across the wafer.
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