Unisys

[Eugene.Leitl at lrz.uni-muenchen.de]

kragen at pobox.com wrote:
 
> But the Tera^H^H^H^HCray MTA is sort of an anomaly --- it's the
> beginning of how all computers will work in a few years, but right
> now, there aren't any other computers that work like it.

Um, are you talking about Tera's hardware threading support? I 
fail to see how this is supposed to be optimal. Why tolerate
costly context switching, if you can allocate a dedicated CPU 
to each asynchronous thread?

Apart from that, best way to use the total silicon real estate of, 
say, a 300 mm wafer, is to make the dies small enough so that 
fabrication defects will only kill a tolerable fraction of them 
(a random hit taking out a mm^2 die is a lot better than killing 
a 4 cm^2 monster die), and use a wafer-local redundant packet 
switched network interconnecting the dies and the individual 
wafers. Combine this with embedded (D|M)RAM with very wide buses and
intrinsic low latency, and you'll see a kBit bus architecture with 
few MByte memory grains, communicating by asynchronous message passing 
with few ns latency.

Not exactly a Beowulf, but not a teratological case, either.