LinuxBIOS (fwd)

[Eugene Leitl]

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---------- Forwarded message ----------
Date: 27 Apr 2001 03:03:17 -0600
From: Eric W. Biederman <ebiederman at lnxi.com>
To: marc.miller at caexmta3.amd.com
Cc: linuxbios at lanl.gov
Subject: Re: LinuxBIOS

marc.miller at caexmta3.amd.com writes:

> One of our software partners encouraged us to find out about LinuxBIOS.
> What info do you need to build support for a particular chipset?

Now that you have gotten heard the practical bottleneck, let me
summarize what is needed  in the general case.  As that is the
question you asked.

LinuxBIOS is a minimal piece of code that initializes the cpu or cpus
in a system, the memory and some other set once chipset values.  It is
just enough to boot a minimal linux kernel loaded from flash.

Because we reuse a general puporse operating system we are not quite
as small as a traditional x86 bios but we are much more capable in
terms of customization.

Everything in linuxBIOS is released under the GPL so everything we do
needs a source of information not restricted by a NDA after the
product is released.  Having a way for developers to cooperate before
an official release is helpful.

Specifics:
For cpu initialization:
 - How to initialize the caches.
 - How to load firmware updates so we can provide those.
 - CPU Model specific registers that must be set (like top of memory,
   and memory type range registers).

For chipset initialization:
 - How to read the serial rom's on the memory
 - How program the memory controller.
 - How to initialize what is effectively the northbridge to the cpu

For chipset usage:
Enough information to write linux drivers for the various other parts.
Generally other people in the linux community will write the drivers
for built in ide controllers pci bridges etc, because they aren't
restricted to just being initialized by the BIOS, but the information
needs to be available or they can't get done. :)

With the AMD-760 chipset documentation publicly available we are
pretty close to what is needed to release non crippled code.  The big
lack is cpu docs.  The L2 cache is the big piece of the puzzle but
I don't think that's the whole story.  Knowing when you generate
memory access bus cycles and when you generate io access bus cpu
cycles looks fairly important as well, as intel cpus only have memory
access bus cycles.

For AMD-760 MP I need to confirm but there appears to be a lack of
documentation on the SMP side publicly available.

As a general rule of thumb we need all of the information a normal
BIOS developer needs, plus we need to be release it under the GPL.

Eric