Beowulf: A theorical approach
glindahl at hpti.com
Thu Jun 22 12:29:55 PDT 2000
> > It's hard to build something that plugs into an Intel-designed CPU bus.
> > Scali tried it and it didn't work so hot.
> At least on Intel hardware, SMP systems have cache coherency in
> the hardware,
Scali's design (and the one I was considering) do not do cache coherency.
They are for message passing systems. As you may gather, I'm a message
passing bigot. Er, evangelist.
Doing cache coherency would be like the SGI O2000, and that would be far
more expensive than what I was talking about. There are approaches that
attack that problem -- see the Isotach research group's work. They are at
UVa, which is why I am aware of them. But not my cup of tea.
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