memory bandwidth on Athlon systems

Richard Walsh rbw at
Wed Jul 19 13:06:07 PDT 2000


The CAS settings on the two boards may be different 
and if the kx133 bus is asynchronous this would add 
a one cycle latency delay to any memory reference.
This reduces throughput across memory reference bursts.

A good reference on this issue (if it applies here)
is at:


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