[Beowulf] Timers and TSC behaviour on SMP/x86

[H.Vidal, Jr.]

If memory serves, TSC sync is an option when configuring a custom
2.4x series kernel.....perhaps this is so for 2.6x as well?

hv

Mikhail Kuzminsky wrote:
> As I remember, TSCs in SMP/x86 are synchronized by Linux kernels at the 
> boot process.
> But the only message (about TSC) I see after Linux boot in dmesg (or 
> /var/log/messages) in SuSE 10.3 w/2.6.22 default kernel on quad-core 
> dual socket Opteron serever is
> 
> "Marking TSC unstable due to TSCs unsynchronized"
> 
> Does it means that RDTSC-based timer (I use it for microbenchmarks) will 
> give wrong results ? :-(
> 
> Some additional information,
> according Software Optimization Guide for AMD Familly 10h Processors
> (quad-core) from Apr 4th, 2008:
> 
> Early each AMD core had own TSC. Now quad-core processors have one 
> common clock source in NorthBridge (BTW, is it in this case integrated 
> into CPU chip - i.e. includes integrated memory controller and support 
> of HT links ? - M.K.) - for all the TSCs of CPUs (cores ? - M.K.).
> 
> The synchronization accuracy should be few tens cycles.
> 
> Mikhail Kuzminsky
> Computer Assistance to Chemical Research Center
> Zelinsky Institute of Organic Chemistry
> Moscow 
> 
> 
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